Floating Point Matrix Multiplication on a Reconfigurable Computing System

C. Sajish, Yogindra Abhyankar (), Shailesh Ghotgalkar and K.A. Venkates
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C. Sajish: Centre for Development of Advanced Computing, Hardware Technology Development Group
Yogindra Abhyankar: Centre for Development of Advanced Computing, Hardware Technology Development Group
Shailesh Ghotgalkar: Centre for Development of Advanced Computing, Hardware Technology Development Group
K.A. Venkates: Alliance Business Academy

A chapter in Current Trends in High Performance Computing and Its Applications, 2005, pp 113-122 from Springer

Abstract: Summary Matrix multiplication is one of the most fundamental and computationally intense operation that is used in a variety of scientific and engineering applications. There are many implementations of this normally O(n3) operation. These implementations differ mainly in terms of algorithms or the platforms. In this paper we present our experimentation of using a reconfigurable computing platform for calling such a routine. This routine use our own developed IEEE-754 compliant double precision hardware library elements implemented on our own developed FPGA based reconfigurable platform to provide acceleration.

Keywords: Matrix Multiplication; FPGA; Reconfigurable Computing System (search for similar items in EconPapers)
Date: 2005
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Persistent link: https://EconPapers.repec.org/RePEc:spr:sprchp:978-3-540-27912-9_11

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DOI: 10.1007/3-540-27912-1_11

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