Challenges and Potentials of Emerging Multicore Architectures

Markus Stürmer (), Gerhard Wellein, Georg Hager, Harald Köstler and Ulrich Rüde
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Markus Stürmer: Universität Erlangen-Nürnberg, Lehrstuhl f. Systemsimulation
Gerhard Wellein: Regionales Rechenzentrum Erlangen
Georg Hager: Regionales Rechenzentrum Erlangen
Harald Köstler: Universität Erlangen-Nürnberg, Lehrstuhl f. Systemsimulation
Ulrich Rüde: Universität Erlangen-Nürnberg, Lehrstuhl f. Systemsimulation

A chapter in High Performance Computing in Science and Engineering, Garching/Munich 2007, 2009, pp 551-566 from Springer

Abstract: Abstract We present performance results on two current multicore architectures, a STI (Sony, Toshiba, and IBM) Cell processor included in the new Playstation™ 3 and a Sun UltraSPARC T2 (“Niagara 2”) machine. On the Niagara 2 we analyze typical performance patterns that emerge from the peculiar way the memory controllers are activated on this chip using the standard STREAM benchmark and a shared-memory parallel lattice Boltzmann code. On the Cell processor we measure the memory bandwidth and run performance tests for LBM simulations. Additionally, we show results for an application in image processing on the Cell processor, where it is required to solve nonlinear anisotropic PDEs.

Date: 2009
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DOI: 10.1007/978-3-540-69182-2_43

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