The Potential of On-Chip Memory Systems for Future Vector Architectures

Hiroaki Kobayashi (), Akihiko Musa (), Yoshiei Sato (), Hiroyuki Takizawa () and Koki Okabe ()
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Hiroaki Kobayashi: Tohoku University, Information Synergy Center
Akihiko Musa: Tohoku University, Graduate School of Information Sciences
Yoshiei Sato: Tohoku University, Graduate School of Information Sciences
Hiroyuki Takizawa: Tohoku University, Information Synergy Center
Koki Okabe: Tohoku University, Information Synergy Center

A chapter in High Performance Computing on Vector Systems 2007, 2008, pp 247-264 from Springer

Abstract: Abstract The most advantageous feature of modern vector systems is their outstanding memory performance compared to scalar systems. This feature brings them to their high-sustained system performance when executing real application codes, which are extensively used in the fields of advanced sciences and engineering [9],[10],[1]. However, recent trends in semiconductor technology generate a strong head wind for vector systems. Thanks to the historical growth rate in on-chip silicon budget, named Moore’s law, processor performance regarding flop/s rates increases remarkably, but memory performance cannot follow it [2]. Regarding vector systems, their bytes/flop rates that show the balance between flop/s performance and memory bandwidth go down from 8 B/flop in 1998, to 4 in 2003, and to 2 in 2007. We have pointed out that reducing the memory bandwidth seriously affects the sustained system performance even in case of vector systems [3], although their absolute performance increases to a certain degree. Memory performance definitely becomes one of key points for design of future highly-efficient vector architectures to survive in an era of multi-core processors.

Keywords: Direct Numerical Simulation; Memory Performance; Vector System; Memory Bandwidth; Sustained Performance (search for similar items in EconPapers)
Date: 2008
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DOI: 10.1007/978-3-540-74384-2_18

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