Lessons Learned from 1-Year Experience with SX-9 and Toward the Next Generation Vector Computing

Hiroaki Kobayashi (), Ryusuke Egawa (), Hiroyuki Takizawa (), Koki Okabe (), Akihiko Musa (), Takashi Soga () and Yoko Isobe ()
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Hiroaki Kobayashi: Tohoku University
Ryusuke Egawa: Tohoku University
Hiroyuki Takizawa: Tohoku University
Koki Okabe: Tohoku University
Akihiko Musa: Tohoku University
Takashi Soga: Tohoku University
Yoko Isobe: NEC Computertehno, Ltd.

A chapter in High Performance Computing on Vector Systems 2009, 2010, pp 3-22 from Springer

Abstract: Abstract This paper discusses the performance of the latest vector-parallel supercomputer system SX-9. First, we report HPC challenge benchmark results of the SX-9 system, in which it achieves 19 top one scores in the 28 tests. In addition, we also discuss some tuning techniques for SX-9. We present case study analysis, in which the effects of code tuning for ADB, a newly introduced, software-controllable on chip cache of SX-9, on the sustained performance is examined by using science and engineering applications. Finally, we present our on-going research work on design of a multi-vector core processor toward the next generation vector computing. Through the experimental results, we confirm that vector caching plays an important role to extract the potential of the multi-vector core processor.

Keywords: Memory Bandwidth; Sustained Performance; Cache Blocking; Loop Unroll; Loop Fusion (search for similar items in EconPapers)
Date: 2010
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Persistent link: https://EconPapers.repec.org/RePEc:spr:sprchp:978-3-642-03913-3_1

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DOI: 10.1007/978-3-642-03913-3_1

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