Complexities of Performance Prediction for Bandwidth-Limited Loop Kernels on Multi-Core Architectures

Jan Treibig (), Georg Hager () and Gerhard Wellein ()
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Jan Treibig: Friedrich-Alexander Universität Erlangen-Nürnberg, Regionales Rechenzentrum Erlangen
Georg Hager: Friedrich-Alexander Universität Erlangen-Nürnberg, Regionales Rechenzentrum Erlangen
Gerhard Wellein: Friedrich-Alexander Universität Erlangen-Nürnberg, Regionales Rechenzentrum Erlangen

A chapter in High Performance Computing in Science and Engineering, Garching/Munich 2009, 2010, pp 3-12 from Springer

Abstract: Abstract The balance metric is a simple approach to estimate the performance of bandwidth-limited loop kernels. However, applying the method to modern multi-core architectures yields unsatisfactory results. This paper analyzes the influence of cache hierarchy design on performance predictions for bandwidth-limited loop kernels on current mainstream processors. We present a diagnostic model with improved predictive power, correcting the limitations of the simple balance metric. The importance of code execution overhead even in bandwidth-bound situations is emphasized.

Keywords: Performance Prediction; Main Memory; Memory Bandwidth; Cache Line; Algorithmic Balance (search for similar items in EconPapers)
Date: 2010
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Persistent link: https://EconPapers.repec.org/RePEc:spr:sprchp:978-3-642-13872-0_1

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DOI: 10.1007/978-3-642-13872-0_1

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