Pseudo-Vectorization and RISC Optimization Techniques for the Hitachi SR8000 Architecture

Georg Hager (), Frank Deserno () and Gerhard Wellein ()
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Georg Hager: Regionales Rechenzentrum Erlangen
Frank Deserno: Regionales Rechenzentrum Erlangen
Gerhard Wellein: Regionales Rechenzentrum Erlangen

A chapter in High Performance Computing in Science and Engineering, Munich 2002, 2003, pp 425-442 from Springer

Abstract: Abstract We demonstrate optimization techniques for the Hitachi SR8000 architecture on CPU and SMP level using selected case studies from real-world codes. Special emphasis is given to a comparison with performance characteristics of other modern RISC and vector CPUs.

Keywords: Access Pattern; Memory Bandwidth; Cache Line; Loop Length; Memory Latency (search for similar items in EconPapers)
Date: 2003
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Persistent link: https://EconPapers.repec.org/RePEc:spr:sprchp:978-3-642-55526-8_34

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DOI: 10.1007/978-3-642-55526-8_34

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