VHDL Specification of a FPGA to Divide and Multiply in GF(2 m )

Mario Alberto García-Martínez () and Guillermo Morales-Luna ()
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Mario Alberto García-Martínez: Instituto Tecnológico de Orizaba, Departamento de Ingeniería Eléctrica-Electrónica
Guillermo Morales-Luna: Instituto Mexicano del Petróleo, Programa de Ingeniería Molecular

A chapter in Finite Fields with Applications to Coding Theory, Cryptography and Related Areas, 2002, pp 164-176 from Springer

Abstract: Abstract Some FPGA’s are designed to compute division and multiplication on Galois fields. FPGA’s are quite cheap programmable logic devices used in digital circuits with the important characteristic of being reprogrammable. Any FPGA can be specified within VHDL which at present is a standard language in the design of digital systems. We describe in VHDL the divider and multiplier basic cells and their whole integration. The structures have scalable systolic architectures. The circuits operate by pipelining; the divider in GF (2 m ) requires 5m − 1 clock cycles while the multiplier 3m − 1. The divider proceeds by the Gaussian triangulation algorithm and is uniform with respect to the irreducible polynomial generating the field. The codes, some simulations and performance measurements are provided.

Keywords: Clock Cycle; Field Programmable Gate Array; Finite Field; Systolic Array; Irreducible Polynomial (search for similar items in EconPapers)
Date: 2002
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Persistent link: https://EconPapers.repec.org/RePEc:spr:sprchp:978-3-642-59435-9_12

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DOI: 10.1007/978-3-642-59435-9_12

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