Improved Systolic Designs for the Iterative Solution of Linear Systems

D. J. Evans and K. Margaritis
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D. J. Evans: University of Technology, Department of Computer Studies
K. Margaritis: University of Technology, Department of Computer Studies

Chapter S18 in Numerical Techniques for Engineering Analysis and Design, 1987, pp 687-703 from Springer

Abstract: Abstract Recent advances in VLSI technology have led to a rapid growth in the research into parallel computer architectures. A major attraction of the emerging VLSI technology is that it will give the scientists and engineers the potential to design, in a cost effective manner, closely related devices and algorithms tailored to particular problem classes (e.g. iterative solution of linear systems of equations is discussed in this paper). An important development in the design of parallel computer architectures is the design of sophisticated microprocessors, (e.g. Transputer, Warp cell) that can be interconnected to form parallel processors, such as Wavefront Arrays, Systolic Arrays, etc. The purpose of this paper is to consider the application of systolic array designs to problems arising in numerical computation, as encountered in many engineering domains. More specifically this paper describes systolic networks for the iterative solution of linear systems of equations using the Jacobi, Gauss-Seidel, JOR and SOR methods. Existing iterative systolic designs are modified to become more area-efficient, two new pipeline architectures are proposed based on an improved matrix-vector multiplication systolic array.

Keywords: Iterative Solution; Systolic Array; Iterative Step; Pipeline Architecture; Synchronization Delay (search for similar items in EconPapers)
Date: 1987
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DOI: 10.1007/978-94-009-3653-9_76

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