Power Minimization and Power Grid Synthesis

Apoorva S. Shastri
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Apoorva S. Shastri: Dr. Vishwanath Karad MIT World Peace University, Institute of Artificial Intelligence

Chapter Chapter 4 in Optimization Methods in VLSI Design, 2025, pp 111-133 from Springer

Abstract: Abstract Modern world integrated circuits are tightly constrained by their power dissipation. Ask process node shrinks day by day we are working in smaller Micron levels. Now the integrated circuits are not only limited by the functionality, but also by the power they dissipate while functioning and in idle mode. This chapter majorly focuses on power minimization and power related synthesis which can help reduce power consumption in integrated circuit design. The techniques discussed in this chapter range from low voltage distribution and high impedance fault detection in connection with high level power Estimation techniques. Fine-grained power modelling of multicore processors, High level power estimation technique in embedded hardware, Fast macro model for substrate in mixed signal VLSI design, Low voltage distribution network technology identification and high impedance fault detection in Power Distribution grid systems are the techniques discussed in this chapter.

Date: 2025
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Persistent link: https://EconPapers.repec.org/RePEc:spr:sprchp:978-981-95-2457-0_4

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DOI: 10.1007/978-981-95-2457-0_4

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