Efficient Testing and Verification Methods

Apoorva S. Shastri
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Apoorva S. Shastri: Dr. Vishwanath Karad MIT World Peace University, Institute of Artificial Intelligence

Chapter Chapter 5 in Optimization Methods in VLSI Design, 2025, pp 135-181 from Springer

Abstract: Abstract When the device is manufactured, lot of analysis is done to check if the modelled input output function resembles to the design on the silicon. Also, manufacturing defects needs to be checked to ensure design Is implemented as required. That’s why this design verification step is a critical one in VLSI design. Chapter discusses about. Techniques used for efficient testing and verification method of the design which was fabricated. This chapter surveys various studies That can detect faults and minimise deviation from the Frontend model and the fabricated design. Such method discussed here is analysis and detection of open gate defects in redundant structures of FinFET SRAM cell, test set construct process for multi missing gate defects in reversible circuits, improved pseudo random fault coverage through inversions. In line is using automation and artificial intelligence to improve the process of verification for multiple FGPA platforms. It’s a process which returns an error code by using neural networks and logic built-in self-test (LBIST). Point is to increase the effectiveness of test content to save time using techniques such as test content compression for scan architecture using modified shuffled shepherd optimization and speed up testing by using probabilistic merit indicators.

Date: 2025
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DOI: 10.1007/978-981-95-2457-0_5

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