Challenges in Full Chip Optimization

Apoorva S. Shastri
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Apoorva S. Shastri: Dr. Vishwanath Karad MIT World Peace University, Institute of Artificial Intelligence

Chapter Chapter 8 in Optimization Methods in VLSI Design, 2025, pp 233-261 from Springer

Abstract: Abstract This chapter discusses a lot of practices that can help minimise, if not remove all the challenges in full chip optimizations. This chapter talks about techniques Which can help a multi objective redundancy hardening task with efficient mapping for independent task on multiple cores. Chapter also walks through Methods of a multi objective learning automation, Techniques that can assistant floor planning and design optimal routing in VLSI circuits using particle swarm optimization, Floor planning of 3D IC design using hybrid optimiser. A novel hybrid method of a chimp Yes. with cuckoo search algorithm for optimal designing of infinite impulse response Filter using high level synthesis. Chapter elaborates on FPGA based hardware accelerator design, also a low-cost BIST design supporting automated testing of fabricated chips. These techniques can help increase efficiency and minimise challenges faced during full chip optimization.

Date: 2025
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Persistent link: https://EconPapers.repec.org/RePEc:spr:sprchp:978-981-95-2457-0_8

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DOI: 10.1007/978-981-95-2457-0_8

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