Preemptive Software Transactional Memory

Emiliano Silvestri (), Simone Economo (), Pierangelo Di Sanzo (), Alessandro Pellegrini () and Francesco Quaglia ()
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Emiliano Silvestri: Department of Computer, Control and Management Engineering Antonio Ruberti (DIAG), University of Rome La Sapienza, Rome, Italy
Simone Economo: Department of Computer, Control and Management Engineering Antonio Ruberti (DIAG), University of Rome La Sapienza, Rome, Italy
Pierangelo Di Sanzo: Department of Computer, Control and Management Engineering Antonio Ruberti (DIAG), University of Rome La Sapienza, Rome, Italy
Alessandro Pellegrini: Department of Computer, Control and Management Engineering Antonio Ruberti (DIAG), University of Rome La Sapienza, Rome, Italy
Francesco Quaglia: Department of Computer, Control and Management Engineering Antonio Ruberti (DIAG), University of Rome La Sapienza, Rome, Italy

No 2017-01, DIAG Technical Reports from Department of Computer, Control and Management Engineering, Universita' degli Studi di Roma "La Sapienza"

Abstract: In state of the art Software Transactional Memory (STM) systems, threads carry out the execution of transactions as non-interruptible tasks. Hence a thread can react to the injection of a higher priority transactional task and take care of its processing only at the end of the currently executed transaction. In this article we pursue a paradigm shift where the execution of an in-memory transaction is carried out as a preemptable task, so that a thread can start processing a higher priority transactional task before finalizing its current transaction. We achieve this goal in an application-transparent manner, by only relying on innovative operating system facilities we include in our preemptive STM architecture. With our approach we are able to reevaluate CPU assignment across transactions along a same thread with period of the order of few tens of microseconds. This is mandatory for an effective priority management architecture given the typically finer-grain nature of in-memory transactions compared to their counterpart in database systems. We integrated our preemptive STM architecture within the TinySTM package, and released it as open source. We also provide the results of an experimental assessment of our proposal based on running a port of the TPC-C benchmark to the STM environment.

Keywords: preemptive stm architecture; software transactional memory; transactional memory; memory transaction; priority transaction; priority level; higher priority; extra tick; timer interrupt; top half; fine grain; time sharing; control flow; variation; transactional thread; scheduler; scheduling; policy (search for similar items in EconPapers)
Date: 2017
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