An Enhancement of Decimation Process using Fast Cascaded Integrator Comb (CIC) Filter

Rozita Teymourzadeh and Masuri Othman

MPRA Paper from University Library of Munich, Germany

Abstract: The over sampling technique has been shown to increase the SNR and is used in many high performance system such as in the ADC for audio and DAT systems. This paper presents the design of the decimation and its VLSI implementation which is the sub-component in the over sampling technique. The design of three main units in the decimation stage that is the Cascaded Integrator Comb (CIC) filter, the associated half band filters and the droop correction are also described. The Verilog HDL code in Xilinx ISE environment has been derived to describe the CIC filter properties and downloaded in to Virtex II FPGA board. In the design of these units, we focus on the trade-off between the speed improvement and the power consumption as well as the silicon area for the chip implementation.

Keywords: Decimation; CIC; comb; Filters; Converters; Sigma Delta A/D conversion; comb filters; decimation filters (search for similar items in EconPapers)
JEL-codes: F14 L7 O14 (search for similar items in EconPapers)
Date: 2006-05-15
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Published in IEEE International Conference on Semiconductor Electronics (ICSE) 10.1109/SMELEC.2006.380749 (2006): pp. 811-815

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