An Overview of the Decimation process and its VLSI implementation
Rozita Teymourzadeh and
Masuri Othman
MPRA Paper from University Library of Munich, Germany
Abstract:
Digital Decimation process plays an important task in communication system. It mostly is applied in transceiver when the frequency reduction is required. However, the decimation process for sigma delta modulator is considered in this research work. The proposed design was simulated using MATLAB software and implemented by hardware description language in Xilinx environment. Furthermore, the proposed advance arithmetic unit is applied to improve the system efficiency.
Keywords: Decimation; CIC; comb; Filters; Converters; Sigma Delta A/D conversion; comb filters; decimation filters (search for similar items in EconPapers)
JEL-codes: F14 L0 L6 L7 O14 (search for similar items in EconPapers)
Date: 2006-02-01, Revised 2006-02-01
References: View complete reference list from CitEc
Citations:
Published in Research Student Seminar SPS2006 (2006): pp. 207-211
Downloads: (external link)
https://mpra.ub.uni-muenchen.de/41945/1/MPRA_paper_41945.pdf original version (application/pdf)
Related works:
This item may be available elsewhere in EconPapers: Search for items with the same title.
Export reference: BibTeX
RIS (EndNote, ProCite, RefMan)
HTML/Text
Persistent link: https://EconPapers.repec.org/RePEc:pra:mprapa:41945
Access Statistics for this paper
More papers in MPRA Paper from University Library of Munich, Germany Ludwigstraße 33, D-80539 Munich, Germany. Contact information at EDIRC.
Bibliographic data for series maintained by Joachim Winter ().