High-Level Synthesis Hardware Accelerators of Integer-pixel Motion Estimation of HEVC on SoC-FPGA Platform

Belal Mohamed, Ahmed Shalaby and Mohammed S. Sayed

2nd Europe – Middle East – North African Regional ITS Conference, Aswan 2019: Leveraging Technologies For Growth from International Telecommunications Society (ITS)

Abstract: Motion estimation entails the major computation complexity load and processing time in HEVC video encoder. Integer-pixel Motion Estimation (IME) consume more than 45% of the processing time. Therefore, this paper presents a High-Level Synthesis Hardware Accelerator for Integerpixel Motion Estimation of HEVC on Xilinx SoC-FPGA Platform. The hardware accelerator is three time faster than the corresponding software implementation with only 100 MHz clock frequency on Xilinx Zynq ZC702 FPGA.

Date: 2019
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Persistent link: https://EconPapers.repec.org/RePEc:zbw:itsm19:201745

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