A hardware approach to value function iteration

Alessandro Peri

Journal of Economic Dynamics and Control, 2020, vol. 114, issue C

Abstract: This paper proposes a novel approach for the computation of dynamic stochastic equilibrium models. We design an FPGA specialized in the computation of a Bellman equation via value function iteration (VFI). Our hardware approach exhibits significant speed gains vis-à-vis GPU-based data-parallelization techniques. The speed gains arise from two layers of parallelism, accessible to hardware developers: instruction-level and pipeline parallelism at the logical resources level. By and large, the paper documents significant computational speed gains from hardware specialization, so far unexplored by the macroeconomic literature.

Keywords: FPGA; Dynamic programming; Pipelining; Growth model; Business cycles (search for similar items in EconPapers)
JEL-codes: C88 (search for similar items in EconPapers)
Date: 2020
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Citations: View citations in EconPapers (1)

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Persistent link: https://EconPapers.repec.org/RePEc:eee:dyncon:v:114:y:2020:i:c:s0165188920300622

DOI: 10.1016/j.jedc.2020.103894

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