A decomposition-based reliability and makespan optimization technique for hardware task graphs
Reza Ramezani,
Yasser Sedaghat,
Mahmoud Naghibzadeh and
Juan Antonio Clemente
Reliability Engineering and System Safety, 2018, vol. 180, issue C, 13-24
Abstract:
This paper presents an approach to optimize the reliability and makespan of hardware task graphs, running on FPGA-based reconfigurable computers, in space-mission computing applications with dynamic soft error rates (SERs). Thus, with rises and falls of the SER, the presented approach dynamically generates a set of solutions that apply redundancy-based fault tolerance (FT) techniques to the running tasks. The set of solutions is generated by decomposing the task graph into multiple subgraphs, applying a multi-objective optimization algorithm to the subgraphs separately, and finally combining and filtering out the obtained solutions of the subgraphs. In this regard, a heuristic has been proposed to decompose task graphs in such a way that a high coverage of the true Pareto set is attained. The experiments show that the presented approach covers 97.37% of the true Pareto set and improves the average computation time of generating the Pareto set from 6.29Â h to 81.86Â ms. In addition, it outperforms the NSGA-II algorithm in terms of the Pareto set coverage and computation time. Additional experiments demonstrate the advantages of the presented approach over the state-of-the-art adaptive FT techniques in dynamic environments.
Keywords: Reliability; Makespan; Fault tolerance; Task graph; FPGA (search for similar items in EconPapers)
Date: 2018
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Citations: View citations in EconPapers (2)
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Persistent link: https://EconPapers.repec.org/RePEc:eee:reensy:v:180:y:2018:i:c:p:13-24
DOI: 10.1016/j.ress.2018.07.007
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