Predicting system failure rates of SRAM-based FPGA on-board processors in space radiation environments

Seunghwa Jung and Jihwan P. Choi

Reliability Engineering and System Safety, 2019, vol. 183, issue C, 374-386

Abstract: Static random-access memory-based field-programmable gate arrays are increasingly being used for on-board processors in space missions. However, they are very susceptible to single event upsets that can generate on-board processor system malfunction or system failures in space radiation environments. This paper presents an on-board processor system adopting Triple Modular Redundancy with the concept of mitigation windows and external scrubber, and then suggests a mathematical model that predicts the on-board processor system failure rate by only using the information of system configuration resources. Our mathematical derivation can estimate on-board processor system reliability as a function of the single event upset rate, the number of mitigation windows, and on-board processor shield thickness. In addition, a guideline of the on-board processor system design is provided for achieving good single event upset mitigation capability and system reliability.

Keywords: SRAM; FPGA; Single event upset; On-board processor; System failure rate; Reliability (search for similar items in EconPapers)
Date: 2019
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Citations: View citations in EconPapers (6)

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Persistent link: https://EconPapers.repec.org/RePEc:eee:reensy:v:183:y:2019:i:c:p:374-386

DOI: 10.1016/j.ress.2018.09.015

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