Model synthesis using boolean expression diagrams

Liu Yang and Antoine Rauzy

Reliability Engineering and System Safety, 2019, vol. 186, issue C, 78-87

Abstract: In this article, we propose a new method for fault tree analysis, called model synthesis, which comes in addition to traditional assessment techniques. It consists in rewriting the fault tree under study, or the set of minimal cutsets extracted from this fault tree, so to make some relevant information emerge.

Keywords: Fault tree synthesis; Boolean expression diagrams; Boolean formulas; System architecture (search for similar items in EconPapers)
Date: 2019
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Persistent link: https://EconPapers.repec.org/RePEc:eee:reensy:v:186:y:2019:i:c:p:78-87

DOI: 10.1016/j.ress.2019.02.019

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