DC Bus Voltage Control of Grid-Side Converter in Permanent Magnet Synchronous Generator Based on Improved Second-Order Linear Active Disturbance Rejection Control

Xuesong Zhou, Yongliang Zhou, Youjie Ma, Luyong Yang, Xia Yang and Bo Zhang
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Xuesong Zhou: Tianjin Key Laboratory for Control Theory and Application in Complicated Systems, Tianjin University of Technology, Tianjin 300384, China
Yongliang Zhou: School of Electrical and Electronic Engineering, Tianjin University of Technology, Tianjin 300384, China
Youjie Ma: Tianjin Key Laboratory for Control Theory and Application in Complicated Systems, Tianjin University of Technology, Tianjin 300384, China
Luyong Yang: School of Electrical and Electronic Engineering, Tianjin University of Technology, Tianjin 300384, China
Xia Yang: School of Electrical and Electronic Engineering, Tianjin University of Technology, Tianjin 300384, China
Bo Zhang: School of Electrical and Electronic Engineering, Tianjin University of Technology, Tianjin 300384, China

Energies, 2020, vol. 13, issue 18, 1-19

Abstract: In the permanent magnet synchronous generator (PMSG), the DC bus voltage fluctuates up and down under the influence of the load and power grid, which greatly affects the safe and reliable work of PMSG. In order to suppress the wide range fluctuation of DC bus voltage under disturbance and enhance its anti-disturbance performance, an optimized DC bus voltage control strategy is proposed by using the improved linear active disturbance rejection control (LADRC) in the voltage outer loop. By considering factors, such as load disturbance and grid voltage mutation as the total disturbance of the system, the improved reduced-order linear expansion state observer (RLSEO) is used to estimate and compensate the total disturbance, which greatly improves the stability of DC bus voltage. Firstly, the mathematical model of grid-side converter is established. On this basis, the LADRC control based on RLESO is designed, which reduces the phase lag of the linear extended state observer (LESO) and enhances the disturbance observation accuracy of the system. Then, a lead lag correction link is added to the total disturbance channel of RLESO to reduce the noise amplification effect of RLESO. Finally, the frequency domain characteristic analysis and stability proof of the improved LADRC control strategy are carried out. The simulation results show that the control strategy proposed in the article has a better control effect on the DC bus voltage.

Keywords: DC bus voltage; grid-side converter; linear active disturbance rejection control; reduced-order linear expansion state observer; correction link; frequency domain analysis (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2020
References: View references in EconPapers View complete reference list from CitEc
Citations: View citations in EconPapers (1)

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