Real-Time Hardware in the Loop Simulation Methodology for Power Converters Using LabVIEW FPGA

Leonel Estrada, Nimrod Vázquez, Joaquín Vaquero, Ángel de Castro and Jaime Arau
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Leonel Estrada: Electronics Department, Instituto Tecnológico Superior del Sur de Guanajuato, Educación Superior 2000, Benito Juárez, 38980 Uriangato, Guanajuato, Mexico
Nimrod Vázquez: Electronics Department, Tecnológico Nacional de México-IT de Celaya, Antonio García Cubas 600, Fovissste, 38010 Celaya, Guanajuato, Mexico
Joaquín Vaquero: Electronics Technology Department, Universidad Rey Juan Carlos, Calle Tulipán, s/n, 28933 Móstoles, Madrid, Spain
Ángel de Castro: Electronics Technology and Communications Department, Universidad Autónoma de Madrid, Ciudad Universitaria de Cantoblanco, 28049 Madrid, Spain
Jaime Arau: Electronics Engineering Department, Tecnológico Nacional de México-CENIDET, Interior Internado, Palmira, 62490 Cuernavaca, Morelos, Mexico

Energies, 2020, vol. 13, issue 2, 1-19

Abstract: Nowadays, the use of the hardware in the loop (HIL) simulation has gained popularity among researchers all over the world. One of its main applications is the simulation of power electronics converters. However, the equipment designed for this purpose is difficult to acquire for some universities or research centers, so ad-hoc solutions for the implementation of HIL simulation in low-cost hardware for power electronics converters is a novel research topic. However, the information regarding implementation is written at a high technical level and in a specific language that is not easy for non-expert users to understand. In this paper, a systematic methodology using LabVIEW software (LabVIEW 2018) for HIL simulation is shown. A fast and easy implementation of power converter topologies is obtained by means of the differential equations that define each state of the power converter. Five simple steps are considered: designing the converter, modeling the converter, solving the model using a numerical method, programming an off-line simulation of the model using fixed-point representation, and implementing the solution of the model in a Field-Programmable Gate Array (FPGA). This methodology is intended for people with no experience in the use of languages as Very High-Speed Integrated Circuit Hardware Description Language (VHDL) for Real-Time Simulation (RTS) and HIL simulation. In order to prove the methodology’s effectiveness and easiness, two converters were simulated—a buck converter and a three-phase Voltage Source Inverter (VSI)—and compared with the simulation of commercial software (PSIM ® v9.0) and a real power converter.

Keywords: design methodology; FPGA; hardware in the loop; LabVIEW; real-time simulation; power converters (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2020
References: View references in EconPapers View complete reference list from CitEc
Citations: View citations in EconPapers (10)

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