Designing Reconfigurable Cyber-Physical Systems Using Unified Modeling Language

Grzegorz Bazydło ()
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Grzegorz Bazydło: Institute of Control & Computation Engineering, University of Zielona Góra, 65-516 Zielona Góra, Poland

Energies, 2023, vol. 16, issue 3, 1-21

Abstract: Technological progress in recent years in the Cyber-Physical Systems (CPSs) area has given designers unprecedented possibilities and computational power, but as a consequence, the modeled CPSs are becoming increasingly complex, hierarchical, and concurrent. Therefore, new methods of CPSs design (especially using abstract modeling) are needed. The paper presents an approach to the CPS control part modeling using state machine diagrams from Unified Modelling Language (UML). The proposed design method attempts to combine the advantages of graphical notation (intuitiveness, convenience, readability) with the benefits of text specification languages (unambiguity, precision, versatility). The UML specification is transformed using Model-Driven Development (MDD) techniques into an effective program in Hardware Description Language (HDL), using Concurrent Finite State Machine (CFSM) as a temporary model. The obtained HDL specification can be analyzed, validated, synthesized, and finally implemented in Field Programmable Gate Array (FPGA) devices. The dynamic, partial reconfiguration (a feature of modern FPGAs) allows for the exchange of a part of the implemented CPS algorithm without stopping the device. But to use this feature, the model must be safe, which in the proposed approach means, that it should possess special idle states, where the control is transferred during the reconfiguration process. Applying the CFSM model greatly facilitates this task. The proposed design method offers efficient graphical modeling of a control part of CPS, and automatic translation of the behavior model into a synthesizable Verilog description, which can be directly implemented in FPGA devices, and dynamically reconfigured as needed. A practical example illustrating the successive stages of the proposed method is also presented.

Keywords: control part of Cyber-Physical System; FPGA; MDD; state machine; UML; Verilog HDL (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2023
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