Design and performance analysis of low power and energy-efficient vedic multipliers

Sadulla Shaik (), Satish Kanapala (), Vallabhuni Vijay () and Chandra Shaker Pittala ()
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Sadulla Shaik: KKR and KSR Institute of Technology and Sciences
Satish Kanapala: Vignan’s Foundation for Science Technology and Research
Vallabhuni Vijay: Department of Electronics and Communication Engineering, Institute of Aeronautical Engineering
Chandra Shaker Pittala: MLR Institute of Technology

International Journal of System Assurance Engineering and Management, 2023, vol. 14, issue 3, No 7, 894-902

Abstract: Abstract This paper explores low-power and energy-efficient multi-bit Vedic Multiplier (VM) architectures at a supply voltage as low as 0.6 V. Energy efficient architectures are a significant concern in VLSI, the Internet of Things (IoT), wireless communications, cryptographic algorithms, and Digital Signal Processing (DSP) circuits. The proposed multipliers are designed with a Vedic multiplication algorithm using the Vedic mathematics formula Urdhva Tiryakbhyam (UT) method. This paper provides design insights and a circuit interaction approach with complementary Metal Oxide Semiconductor (CMOS) and FinFET technologies for designing VM blocks. All the proposed designs show better power delay product (PDP) characteristics at VDD 0.6 V. FinFET-based 8-bit VM design has lower power consumption and PDP of 36.5% and 55.8%, respectively, compared with CMOS 8-bit VM design at a supply voltage of 0.6 V.

Keywords: Adders; FinFET; GDI logic; Pass transistor logic (PTL); Urdhva Tiryakbhyam; Vedic multiplier (search for similar items in EconPapers)
Date: 2023
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DOI: 10.1007/s13198-023-01889-1

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