An innovative LSB image steganography system for multi-image concealment using hardware-software co-design

Ahmad F. Fathil (), Harith G. Ayoub () and Zaid A. Abdulrazzaq ()

International Journal of Innovative Research and Scientific Studies, 2025, vol. 8, issue 3, 1793-1810

Abstract: This paper presents an accelerated image steganography technique utilizing Least Significant Bit (LSB) algorithms implemented on FPGA hardware to conceal and retrieve three hidden images within an RGB cover image. The embedding process uses an XOR operation between the secret bit and the cover pixel's least significant bit (LSB): if the result is zero, the bits are identical, and no change is needed; if the result is one, the secret bit replaces the LSB of the cover pixel. Two system designs were developed to evaluate acceleration: a hardware implementation on a Xilinx ZYNQ-7020 FPGA using XSG programming and a software implementation coded in MATLAB, running on a Core i7-10750H CPU @ 2.60 GHz with 8 GB RAM. The proposed system was evaluated using various performance metrics, including histogram analysis, PSNR, MSE, BER, SSIM, CCR, execution time, operating frequency, and throughput. Experimental results showed clear, accurate image retrieval with significant acceleration: the software execution time was 0.153 seconds, while the FPGA hardware achieved 23.405 microseconds, yielding a speedup factor of approximately 6537×.

Keywords: FPGA; LSB; Multiple images; Steganography. (search for similar items in EconPapers)
Date: 2025
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Persistent link: https://EconPapers.repec.org/RePEc:aac:ijirss:v:8:y:2025:i:3:p:1793-1810:id:6887

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