Performance Evaluation of a Three Phase Nine Level Inverter with Reduced Switch Count

Balamurugan C.R. (), Natarajan S.P. and Pavithra S.
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Balamurugan C.R.: Department of Electrical & Electronics Engineering, Arunai Engineering College, Tiruvannamalai, Tamilnadu, India
Natarajan S.P.: Department of EIE, Annamalai University, Chidambaram, Tamil nadu, India
Pavithra S.: Department of Electrical & Electronics Engineering, Arunai Engineering College, Tiruvannamalai, Tamilnadu, India

Scientific Review, 2015, vol. 1, issue 1, 5-15

Abstract: This paper presents a three phase nine level cascaded H-bridge (CHB) multilevel inverter with RL load. A sinusoidal and trapezoidal PWM method is used to achieve minimum total harmonics distortion (THD) in the output current of multilevel inverters. The analysis of the output current harmonics is carried out and compared with the seven level conventional cascaded H-bridge inverters. The proposed inverter is verified through simulation and the simulation results are compared with the conventional multilevel inverter. From the result the proposed inverter offers much less total harmonic distortion.

Keywords: THD; CHB; Three phase inverter. (search for similar items in EconPapers)
Date: 2015
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