A Systemc Cache Simulator for a Multiprocessor Shared Memory System

Alfred Mutanga

Academic Journal of Interdisciplinary Studies, 2013, vol. 2

Abstract: In this research we built a SystemC Level-1 data cache system in a distributed shared memory architectural environment, with each processor having its own local cache. Using a set of Fast-Fourier Transform and Random trace files we evaluated the cache performance, based on the number of cache hits/misses, of the caches using snooping and directory-based cache coherence protocols. A series of experiments were carried out, with the results of the experiments showing that the directory-based MOESI cache coherency protocol has a performance edge over the snooping Valid-Invalid cache coherency protocol.

Date: 2013
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Persistent link: https://EconPapers.repec.org/RePEc:bjz:ajisjr:286

DOI: 10.5901/ajis.2013.v2n7p85

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