Design of Alu Design Using 2T XOR Gate AND Decoder

M. Roopa and P. Murali Krishna

International Journal of Scientific Research in Science and Technology, 2024, vol. 11, issue 4, 144-151

Abstract: There is a model for an 8-bit Arithmetic Logic Unit (ALU) that uses the Gate Diffusion Input (GDI) approach. Low power consumption and a significantly reduced transistor count are achieved by implementing the GDI approach in ALU architecture. can lower chip-area and power consumption, two of the key factors in the design of digital VLSIs. In this architecture, the entire adder and subtractor are implemented using 3T XOR. Furthermore, the design also makes use of a unique 1-to-8 de multiplexer circuit. An 8-bit ALU that can execute eight distinct operations was eventually constructed after a significant number of research articles were examined and compared with other logic families.[3][4] Within the suggested approach In the electronics sector, power dissipation and circuit area are the primary concerns. The full adder, subtractor, and ALU circuits in this study are developed using a novel 2T XOR gate. Tanner EDA with 250 nm is used to perform the simulation results. It is evident from the data that the suggested design uses fewer transistors while consuming less power.[5][6]

Keywords: Full Adder; Subtractor; ALU Circuits; XOR Gate (search for similar items in EconPapers)
Date: 2024
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Persistent link: https://EconPapers.repec.org/RePEc:etm:ijsrst:v11:y2024:i4:id:267

DOI: 10.32628/IJSRST24114116

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