Enhancing Power Efficiency in FIR Filter VLSI Architecture for Seismic Signal Processing with Clock Gating

K. Rushendrababu, S. Siddaiah, V. Sai Siva Durga, P. Susmitha and Y. Vamsidhar Rao

International Journal of Scientific Research in Science and Technology, 2025, vol. 12, issue 2, 866-874

Abstract: For real-time seismic signal processing in a seismic alert system, finite impulse response (FIR) filters must exhibit low complexity, high processing speed, and adaptability. A widely used approach to reducing hardware complexity in digital FIR filters involves minimizing logic operators (LOs) and logic depths (LDs) through common sub-expression elimination (CSE). This paper presents a novel matrix-grouped CSE (MCSE) technique that outperforms conventional CSE methods by significantly reducing LOs and LDs. Additionally, a half-unit biased (HUB) rounding method is incorporated to mitigate truncation errors while maintaining design simplicity. To further optimize performance, the cut-set retiming technique is employed to minimize the critical-path delay (CPD). Two hardware-efficient FIR filter architectures—Design I and Design II—are introduced, integrating the proposed canonical signed digit (CSD)-based MCSE algorithm, HUB rounding, and cut-set retiming. Notably, Design II demonstrates a hardware-efficient implementation of a reconfigurable FIR filter. The architectures are implemented on both FPGA and ASIC platforms for hardware validation.

Keywords: Finite impulse response (FIR); half-unit biased (HUB); canonical signed digit (CSD); common sub-expression elimination (CSE); seismic signal (search for similar items in EconPapers)
Date: 2025
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Persistent link: https://EconPapers.repec.org/RePEc:etm:ijsrst:v12:y2025:i2:id:738

DOI: 10.32628/IJSRST251222634

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