Enhancing Circuit Security and Functionality through Probabilistic Majority Voter (PMV) Circuit Integration in Integrated Circuit Design

K R Surendra, M Faiza Farhath, Sneha Agarwal, Madhireddy Venkata Narasimha Reddy, Mandireddy Udaykiran and M Bharath Kumar

International Journal of Scientific Research in Science and Technology, 2026, vol. 13, issue 2, 367-377

Abstract: This work presents the design and progressive enhancement of a probabilistic logic circuit using XOR-based randomization and majority voting principles to achieve stable, reliable, and energy-efficient digital computation. The proposed architecture is developed through multiple design stages, beginning with a basic XOR–majority logic configuration, followed by a MUX-controlled majority logic stage, an optimized XOR–majority logic stage, an inversion-feedback-based majority logic stage, and finally a NAND–AND optimized majority logic configuration. Each stage integrates logic gates such as XOR, AND, NAND, and NOT to effectively combine probabilistic behavior with deterministic validation. In all stages, XOR logic introduces controlled randomness, while a three-input majority voter stabilizes the output under uncertain input conditions. An adaptive control signal (K) and inversion feedback further enhance output stability and reduce noise sensitivity. Simulation results obtained using Microwind analog simulation show a clear improvement in power efficiency across the design stages. The measured power dissipation is 19.845 µW for the basic XOR–majority logic, reduces to 15.264 µW for the MUX-controlled configuration, increases to 21.054 µW in the optimized XOR–majority stage due to higher switching activity, and is subsequently reduced to 16.632 µW using inversion feedback. The final NAND–AND optimized majority logic achieves a low power consumption of 15.810 µW while maintaining high output stability. The results demonstrate that integrating probabilistic logic with majority control significantly improves fault tolerance, noise immunity, and energy efficiency. This design approach effectively addresses real-world uncertainty in digital circuits and is well suited for low-power, fault-tolerant, and adaptive computing applications.

Keywords: Probabilistic Logic; Majority Voter; Low-Power VLSI; Fault-Tolerant Circuits; Hardware Security; Energy-Efficient Design (search for similar items in EconPapers)
Date: 2026
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Persistent link: https://EconPapers.repec.org/RePEc:etm:ijsrst:v13:y2026:i2:id:1461

DOI: 10.32628/IJSRST261336

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