Transistor-Optimized FinFet Full Adder for Low-Power and High-Speed VLSI

A. Krishna Mohan, E Giri, Koya Lohitha, Chinthakunta Pranadeep Reddy, Gajula Pavankalyan and Matta Lokesh Reddy

International Journal of Scientific Research in Science and Technology, 2026, vol. 13, issue 2, 444-452

Abstract: With the aggressive scaling of semiconductor technologies, the design of low-power and high-speed arithmetic circuits has become a critical challenge in Very Large-Scale Integration (VLSI) systems. The full adder is a fundamental building block extensively used in arithmetic logic units, digital signal processing, and microprocessor architectures. Conventional CMOS and higher-transistor-count FinFET full adders suffer from increased power consumption, larger area, and higher delay due to excessive switching activity and parasitic capacitances. To overcome these limitations, this paper proposes an ultra-low-power 5-transistor (5T) FinFET-based full adder utilizing pass-transistor logic. The proposed design is simulated using the Tanner SPICE tool and compared with existing 10T, 8T, and 6T FinFET full adders. Simulation results show that the proposed 5T FinFET full adder achieves a propagation delay of approximately 20 ps, an average power consumption of 58.48 pW, and energy consumption of 11.69 × 10⁻²¹ J, while maintaining near full-swing output voltages of 0.8 V for both Sum and Carry outputs. Compared to the 10T FinFET full adder, the proposed design exhibits significant reductions in power consumption, energy usage, and transistor count, making it highly suitable for low-power and energy-efficient VLSI applications.

Keywords: FinFET; Full Adder; Low-Power VLSI; Tanner SPICE; Pass Transistor Logic; Energy-Efficient Design (search for similar items in EconPapers)
Date: 2026
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Persistent link: https://EconPapers.repec.org/RePEc:etm:ijsrst:v13:y2026:i2:id:1469

DOI: 10.32628/IJSRST2613315

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