Asymmetric Multilevel Inverter Topology and Its Fault Management Strategy for High-Reliability Applications

Mohammad Fahad, Mohd Tariq, Adil Sarwar, Mohammad Modabbir, Mohd Aman Zaid, Kuntal Satpathi, Reyaz Hussan Md, Mohammad Tayyab, Basem Alamri and Ahmad Alahmadi
Additional contact information
Mohammad Fahad: Department of Electrical Engineering, Aligarh Muslim University, Aligarh, Uttar Pradesh 202002, India
Mohd Tariq: Department of Electrical Engineering, Aligarh Muslim University, Aligarh, Uttar Pradesh 202002, India
Adil Sarwar: Department of Electrical Engineering, Aligarh Muslim University, Aligarh, Uttar Pradesh 202002, India
Mohammad Modabbir: Department of Electrical Engineering, Aligarh Muslim University, Aligarh, Uttar Pradesh 202002, India
Mohd Aman Zaid: Department of Electrical Engineering, Aligarh Muslim University, Aligarh, Uttar Pradesh 202002, India
Kuntal Satpathi: Energy Exemplar (Singapore) Pte Ltd., 9 Battery Road, Singapore 049910, Singapore
Reyaz Hussan Md: Department of Electrical Engineering, Aligarh Muslim University, Aligarh, Uttar Pradesh 202002, India
Mohammad Tayyab: Department of Electrical Engineering, Aligarh Muslim University, Aligarh, Uttar Pradesh 202002, India
Basem Alamri: Department of Electrical Engineering, College of Engineering, Taif University, Taif 21944, Saudi Arabia
Ahmad Alahmadi: Department of Electrical Engineering, College of Engineering, Taif University, Taif 21944, Saudi Arabia

Energies, 2021, vol. 14, issue 14, 1-21

Abstract: As the applications of power electronic converters increase across multiple domains, so do the associated challenges. With multilevel inverters (MLIs) being one of the key technologies used in renewable systems and electrification, their reliability and fault ride-through capabilities are highly desirable. While using a large number of semiconductor components that are the leading cause of failures in power electronics systems, fault tolerance against switch open-circuit faults is necessary, especially in remote applications with substantial maintenance penalties or safety-critical operation. In this paper, a fault-tolerant asymmetric reduced device count multilevel inverter topology producing an 11-level output under healthy conditions and capable of operating after open-circuit fault in any switch is presented. Nearest-level control (NLC) based Pulse width modulation is implemented and is updated post-fault to continue operation at an acceptable power quality. Reliability analysis of the structure is carried out to assess the benefits of fault tolerance. The topology is compared with various fault-tolerant topologies discussed in the recent literature. Moreover, an artificial intelligence (AI)-based fault detection method is proposed as a machine learning classification problem using decision trees. The fault detection method is successful in detecting fault location with low computational requirements and desirable accuracy.

Keywords: multilevel inverters; power electronics; fault tolerance; fault detection (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2021
References: View complete reference list from CitEc
Citations: View citations in EconPapers (4)

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