Implementation of an FPGA-Based Current Control and SVPWM ASIC with Asymmetric Five-Segment Switching Scheme for AC Motor Drives

Ming-Fa Tsai, Chung-Shi Tseng and Po-Jen Cheng
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Ming-Fa Tsai: Department of Electrical Engineering, Minghsin University of Science and Technology, No. 1, Xinxing Rd., Xinfeng, Hsinchu 30401, Taiwan
Chung-Shi Tseng: Department of Electrical Engineering, Minghsin University of Science and Technology, No. 1, Xinxing Rd., Xinfeng, Hsinchu 30401, Taiwan
Po-Jen Cheng: Department of Electrical Engineering, Minghsin University of Science and Technology, No. 1, Xinxing Rd., Xinfeng, Hsinchu 30401, Taiwan

Energies, 2021, vol. 14, issue 5, 1-23

Abstract: This paper presents the design and implementation of an application-specific integrated circuit (ASIC) for a discrete-time current control and space-vector pulse-width modulation (SVPWM) with asymmetric five-segment switching scheme for AC motor drives. As compared to a conventional three-phase symmetric seven-segment switching SVPWM scheme, the proposed method involves five-segment two-phase switching in each switching period, so the inverter switching times and power loss can be reduced by 33%. In addition, the produced PWM signal is asymmetric with respect to the center-symmetric triangular carrier wave, and the voltage command signal from the discrete-time current control output can be given in each half period of the PWM switching time interval, hence increasing the system bandwidth and allowing the motor drive system with better dynamic response. For the verification of the proposed SVPWM modulation scheme, the current control function in the stationary reference frame is also included in the design of the ASIC. The design is firstly verified by using PSIM simulation tool. Then, a DE0-nano field programmable gate array (FPGA) control board is employed to drive a 300W permanent-magnet synchronous motor (PMSM) for the experimental verification of the ASIC.

Keywords: SVPWM ASIC; asymmetric five-segment switching; AC motor drives; current control; FPGA control (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2021
References: View references in EconPapers View complete reference list from CitEc
Citations: View citations in EconPapers (1)

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