A Novel Multilevel Inverter Topology Generating a 19-Level Output Regulated by the PD-PWM Method

Sofia Lemssaddak, Abdelhafid Ait Elmahjoub, Mohamed Tabaa (), Adnane El-Alami and Mourad Zegrari
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Sofia Lemssaddak: Digital Engineering for Leading Technology and Automation Laboratory (DELTA Lab), ENSAM Casablanca, Hassan II University of Casablanca, Casablanca 20360, Morocco
Abdelhafid Ait Elmahjoub: Digital Engineering for Leading Technology and Automation Laboratory (DELTA Lab), ENSAM Casablanca, Hassan II University of Casablanca, Casablanca 20360, Morocco
Mohamed Tabaa: Multidisciplinary Laboratory of Research and Innovation (LPRI), Moroccan School of Engineering Sciences (EMSI), Casablanca 20250, Morocco
Adnane El-Alami: Digital Engineering for Leading Technology and Automation Laboratory (DELTA Lab), ENSAM Casablanca, Hassan II University of Casablanca, Casablanca 20360, Morocco
Mourad Zegrari: Digital Engineering for Leading Technology and Automation Laboratory (DELTA Lab), ENSAM Casablanca, Hassan II University of Casablanca, Casablanca 20360, Morocco

Energies, 2025, vol. 18, issue 13, 1-24

Abstract: Traditional multilevel inverter topologies, such FC, NPC, and CHB, have a few significant disadvantages. They need a great number of parts, which raises the complexity, expense, and switching losses. Furthermore, their intricate control schemes make voltage balancing and synchronization challenging. Lastly, under some circumstances, they experience severe harmonic distortion, necessitating the inclusion of expensive filters to enhance signal quality. This paper proposes a novel multilevel converter topology that uses the phase-disposition PWM (PD-PWM) technique to control a 19-level output. This new configuration maintains performance comparable to the CHB-MLI reference while using fewer switches, simplifying control, and reducing costs. Our approach is based on extensive simulations conducted in the MATLAB Simulink environment, with results compared to the CHB-MLI. A low-pass filter is added to improve the output voltage quality, reducing the THD% to 1.33%. This strategy offers several advantages, including simpler control, lower costs, increased reliability, and higher-quality output. The system was replicated using MATLAB Simulink and validated through hardware-in-the-loop (HIL) testing. The HIL method ensures real-world testing without causing damage to the hardware. The integrated system includes sensors and necessary hardware for a comprehensive energy management solution.

Keywords: PD-PWM: phase-disposition pulse width modulation; CHB-MLI: cascaded H-bridge multilevel inverter; THD: total harmonic distortion; hardware in the loop (search for similar items in EconPapers)
JEL-codes: Q Q0 Q4 Q40 Q41 Q42 Q43 Q47 Q48 Q49 (search for similar items in EconPapers)
Date: 2025
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