A Verilog Programming Learning Assistant System Focused on Basic Verilog with a Guided Learning Method

Pin-Chieh Hsieh, Tzu-Lun Fang, Shaobo Jin, Yuyan Wang, Nobuo Funabiki () and Yu-Cheng Fan ()
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Pin-Chieh Hsieh: Department of Electronic Engineering, National Taipei University of Technology, Taipei 10608, Taiwan
Tzu-Lun Fang: Department of Electronic Engineering, National Taipei University of Technology, Taipei 10608, Taiwan
Shaobo Jin: Department of Information and Communication Systems, Okayama University, Okayama 700-8530, Japan
Yuyan Wang: Department of Information and Communication Systems, Okayama University, Okayama 700-8530, Japan
Nobuo Funabiki: Department of Information and Communication Systems, Okayama University, Okayama 700-8530, Japan
Yu-Cheng Fan: Department of Electronic Engineering, National Taipei University of Technology, Taipei 10608, Taiwan

Future Internet, 2025, vol. 17, issue 8, 1-34

Abstract: With continuous advancements in semiconductor technology, mastering efficient designs of high-quality and advanced chips has become an important part of science and technology education. Chip performances will determine the futures of various aspects of societies. However, novice students often encounter difficulties in learning digital chip designs using Verilog programming , a common hardware design language. An efficient self-study system for supporting them that can offer various exercise problems, such that any answer is marked automatically, is in strong demand. In this paper, we design and implement a web-based Verilog programming learning assistant system ( VPLAS ), based on our previous works on software programming. Using a heuristic and guided learning method, VPLAS leads students to learn the basic circuit syntax step by step, until they acquire high-quality digital integrated circuit design abilities through self-study. For evaluation, we assign the proposal to 50 undergraduate students at the National Taipei University of Technology, Taiwan, who are taking the introductory chip-design course, and confirm that their learning outcomes using VPLAS together are far better than those obtained when following a traditional method. In our final statistics, students achieved an average initial accuracy rate of over 70% on their first attempts at answering questions after learning through our website’s tutorials. With the help of the system’s instant automated grading and rapid feedback, their average accuracy rate eventually exceeded 99%. This clearly demonstrates that our system effectively enables students to independently master Verilog circuit knowledge through self-directed learning.

Keywords: Verilog; online learning; guided learning; heuristic learning; programming learning assistant system; Verilog web-based (search for similar items in EconPapers)
JEL-codes: O3 (search for similar items in EconPapers)
Date: 2025
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