A New Memory-Processing Unit Model Based on Spiking Neural P Systems with Dendritic and Synaptic Behavior for Kronecker Matrix–Matrix Multiplication

Luis Garcia, Esteban Ramse Anides, Eduardo Vazquez, Linda Karina Toscano, Gabriel Sanchez, Juan Gerardo Avalos () and Giovanny Sanchez ()
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Luis Garcia: Instituto Politécnico Nacional, ESIME Culhuacan, Av. Santa Ana No. 1000, Ciudad de México 04260, Mexico
Esteban Ramse Anides: Instituto Politécnico Nacional, ESIME Culhuacan, Av. Santa Ana No. 1000, Ciudad de México 04260, Mexico
Eduardo Vazquez: Instituto Politécnico Nacional, ESIME Culhuacan, Av. Santa Ana No. 1000, Ciudad de México 04260, Mexico
Linda Karina Toscano: Instituto Politécnico Nacional, ESIME Culhuacan, Av. Santa Ana No. 1000, Ciudad de México 04260, Mexico
Gabriel Sanchez: Instituto Politécnico Nacional, ESIME Culhuacan, Av. Santa Ana No. 1000, Ciudad de México 04260, Mexico
Juan Gerardo Avalos: Instituto Politécnico Nacional, ESIME Culhuacan, Av. Santa Ana No. 1000, Ciudad de México 04260, Mexico
Giovanny Sanchez: Instituto Politécnico Nacional, ESIME Culhuacan, Av. Santa Ana No. 1000, Ciudad de México 04260, Mexico

Mathematics, 2025, vol. 13, issue 22, 1-10

Abstract: Currently, Kronecker Matrix–Matrix Multiplication play a crucial role in many advanced applications across science and engineering, such as Quantum Computing (Tensor Representation of Quantum States, Quantum Gate Construction), Machine Learning and Data Science (Kernel Methods, Tensor Decompositions), and Signal and Image Processing (Multi-dimensional Filtering, Compression Algorithms). However, the implementation of the Kronecker Matrix–Matrix Multiplication increasingly relies on systems with enhanced computational capabilities. Specifically, current implementations expend large amounts of external memory and requires a large number of processing units to perform this operation. As is commonly acknowledged, cutting-edge high-performance computing schemes still faces limitations in terms of energy and performance due to the bottleneck in data transfer between processing units and memory. To mitigate this limitation, memory processing units (MPUs) enable direct computation on in-memory data, reducing latency and eliminating the need for data transfer. On the other hand, spiking neural P systems, with their inherent parallelism and distributed processing capabilities, are therefore well-suited as foundational components for implementing such memory architectures efficiently. From the mathematical point of view, we present for the first time a neural, synaptic, and dendritic model to support the Kronecker Matrix–Matrix multiplication. To this end, the proposed spiking neural P system with their cutting-edge variants, such as anti-spikes, communication on request, synaptic weights, and dendritic–axonal delays, facilitates the creation of neural memory cells and spike-based routers. Hence, these elements potentially allow the design of novel processing memory architectures that markedly enhance data transfer efficiency between computational units and memory.

Keywords: spiking neural P systems; memory-processing unit; processing-in-memory; FPGA (search for similar items in EconPapers)
JEL-codes: C (search for similar items in EconPapers)
Date: 2025
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