Performance Parameter Evaluation of 7nm FinFET by Tuning Metal Work Function and High K Dielectrics

Sarika Madhukar Jagtap and Vitthal Janardan Gond
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Sarika Madhukar Jagtap: MVPS's College of Engineering, Nashik, India
Vitthal Janardan Gond: MET's Institute of Engineering, Nashik, India

International Journal of Natural Computing Research (IJNCR), 2021, vol. 10, issue 3, 12-28

Abstract: The scrambling of MOSFET below 22nm, 14nm, unwanted Short Channel Effects (SCE) like punch through, drain-induced barrier lowering (DIBL), along with huge leakage current are flowing through the device, which is not recognized for better performance. Multi-gate MOSFET generally measured as Fin-FET is the best substitute vital to stunned short channel effects. The work highlights results of the current-voltage electrical characteristics of the n-channel triple gate Fin-FET gatherings. The paper focuses on the study of geometry-based device design of Fin-FET by changing high k dielectrics materials from silicon SiO2 (3.9), Hafnium Oxide (HfO2), and metal gate work function ranging from 4.1eV to 4.5eV. The approach and simulation of 3Dimensional Fin-FET is carried to evaluate the better performance parameters of device for change in gate length by deploying different dielectrics materials. The effect on ratio of on current (ION) and off current (IOFF), threshold voltage (VTH), subthreshold slope (SS), and drain-induced barrier lowering (DIBL) is observed.

Date: 2021
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Persistent link: https://EconPapers.repec.org/RePEc:igg:jncr00:v:10:y:2021:i:3:p:12-28

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