Low-Power Approximate Unsigned and Signed Multipliers with Configurable Error Recovery

K. Nagi Reddy, K. Ruchitha, B. Sai Srinivas, D. Venu and K. Vinay

International Journal of Scientific Research in Computer Science, Engineering and Information Technology, 2024, vol. 10, issue 3, 109-117

Abstract: In the field of Digital Signal Processing and similar applications, Approximate circuits are being explored as a means to enhance performance and energy efficiency by sacrificing a degree of accuracy. Within these circuits, Multipliers play a crucial role and are being investigated for their potential impact on overall system optimization. In this paper, a novel approximate multiplier with a low power consumption and a short critical path is proposed for high-performance DSP applications. This multiplier leverages a newly designed approximate adder that limits its carry propagation to the nearest neighbours for fast partial product accumulation. Different levels of accuracy can be achieved by using either OR gates or the proposed approximate adder in a configurable error recovery. The multipliers using these two error reduction strategies are referred to as Approximate Multiplier 1 (AM1) and Approximate Multiplier 2 (AM2), respectively. Both AM1 and AM2 have a low mean error distance, i.e., most of the errors are not significant in magnitude. Compared with a Unsigned multiplication multiplier, with the signed multiplication. The signed multiplication tends to have lower power consumption is observed. By utilizing an appropriate error recovery, the proposed approximate multipliers achieve similar processing accuracy as traditional exact multipliers, but with significant improvements in power.

Keywords: Multiplier; Digital Signal Processing; Digital Systems; Carry Propagation Adder (search for similar items in EconPapers)
Date: 2024
Note: Article URL: https://ijsrcseit.com/home/article/view/CSEIT2410311
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Persistent link: https://EconPapers.repec.org/RePEc:jbh:ijsrcs:v10:y2024:i3:id:181

DOI: 10.32628/CSEIT2410311

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