FINITE FIELD MULTIPLIER ACCUMULATOR UNIT BY USING SUB WORD PARALLEL ARCHITECTURE

Abhinav V. Deshpande
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Abhinav V. Deshpande: School of Electronics Engineering (SENSE) Vellore Institute of Technology (VIT), Vellore, India

Noble International Journal of Scientific Research, 2019, vol. 3, issue 11, 109-116

Abstract: This research paper presents a flexible Galois Field Multiplier Accumulator Unit (MAC), which can be used as a computational block in a digital signal processor (DSP). The MAC unit can be used to perform the process of error detection through a parallel computation of the Cyclic Redundancy Checks (CRC). We propose a Galois Field MAC based algorithm in order to perform the parallel computation of an m-bit CRC by using the I bits of the message at a time, where i ? m. Handling less than m bits in the parallel enables a trade off by significantly reducing the hardware area and delay of the computational block. The MAC can also be used to perform the error correction process by employing the Reed Solomon Codes. It uses a sub word parallel architecture in order to optimize the performance of the CRC algorithm and the Reed Solomon encoding/decoding. Thus, it enables a programmable solution to a large variety of applications by employing the error control coding techniques in the communication and consumer electronics field.

Keywords: Finite Field Multiplier Accumulator Unit; Sub Word Parallel Architecture; Reed Solomon Codes. (search for similar items in EconPapers)
Date: 2019
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