Ultrashort vertical-channel MoS2 transistor using a self-aligned contact

Liting Liu, Yang Chen, Long Chen, Biao Xie, Guoli Li (), Lingan Kong, Quanyang Tao, Zhiwei Li, Xiaokun Yang, Zheyi Lu, Likuan Ma, Donglin Lu, Xiangdong Yang and Yuan Liu ()
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Liting Liu: School of Physics and Electronics, Hunan University
Yang Chen: School of Physics and Electronics, Hunan University
Long Chen: School of Physics and Electronics, Hunan University
Biao Xie: School of Physics and Electronics, Hunan University
Guoli Li: School of Physics and Electronics, Hunan University
Lingan Kong: School of Physics and Electronics, Hunan University
Quanyang Tao: School of Physics and Electronics, Hunan University
Zhiwei Li: School of Physics and Electronics, Hunan University
Xiaokun Yang: School of Physics and Electronics, Hunan University
Zheyi Lu: School of Physics and Electronics, Hunan University
Likuan Ma: School of Physics and Electronics, Hunan University
Donglin Lu: School of Physics and Electronics, Hunan University
Xiangdong Yang: Ningbo University of Technology
Yuan Liu: School of Physics and Electronics, Hunan University

Nature Communications, 2024, vol. 15, issue 1, 1-7

Abstract: Abstract Two-dimensional (2D) semiconductors hold great promises for ultra-scaled transistors. In particular, the gate length of MoS2 transistor has been scaled to 1 nm and 0.3 nm using single wall carbon nanotube and graphene, respectively. However, simultaneously scaling the channel length of these short-gate transistor is still challenging, and could be largely attributed to the processing difficulties to precisely align source-drain contact with gate electrode. Here, we report a self-alignment process for realizing ultra-scaled 2D transistors. By mechanically folding a graphene/BN/MoS2 heterostructure, source-drain metals could be precisely aligned around the folded edge, and the channel length is only dictated by heterostructure thickness. Together, we could realize sub-1 nm gate length and sub-50 nm channel length for vertical MoS2 transistor simultaneously. The self-aligned device exhibits on-off ratio over 105 and on-state current of 250 μA/μm at 4 V bias, which is over 40 times higher compared to control sample without self-alignment process.

Date: 2024
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DOI: 10.1038/s41467-023-44519-x

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