Large-scale sub-5-nm vertical transistors by van der Waals integration

Xiaokun Yang, Rui He, Zheyi Lu, Yang Chen, Liting Liu, Donglin Lu, Likuan Ma, Quanyang Tao, Lingan Kong, Zhaojing Xiao, Songlong Liu, Zhiwei Li, Shuimei Ding, Xiao Liu, Yunxin Li, Yiliu Wang, Lei Liao and Yuan Liu ()
Additional contact information
Xiaokun Yang: Hunan University
Rui He: Hunan University
Zheyi Lu: Hunan University
Yang Chen: Hunan University
Liting Liu: Hunan University
Donglin Lu: Hunan University
Likuan Ma: Hunan University
Quanyang Tao: Hunan University
Lingan Kong: Hunan University
Zhaojing Xiao: Hunan University
Songlong Liu: Hunan University
Zhiwei Li: Hunan University
Shuimei Ding: Hunan University
Xiao Liu: Hunan University
Yunxin Li: Hunan University
Yiliu Wang: Hunan University
Lei Liao: Hunan University
Yuan Liu: Hunan University

Nature Communications, 2024, vol. 15, issue 1, 1-8

Abstract: Abstract Vertical field effect transistor (VFET), in which the semiconductor is sandwiched between source/drain electrodes and the channel length is simply determined by the semiconductor thickness, has demonstrated promising potential for short channel devices. However, despite extensive efforts over the past decade, scalable methods to fabricate ultra-short channel VFETs remain challenging. Here, we demonstrate a layer-by-layer transfer process of large-scale indium gallium zinc oxide (IGZO) semiconductor arrays and metal electrodes, and realize large-scale VFETs with ultra-short channel length and high device performance. Within this process, the oxide semiconductor could be pre-deposited on a sacrificial wafer, and then physically released and sandwiched between metals, maintaining the intrinsic properties of ultra-scaled vertical channel. Based on this lamination process, we realize 2 inch-scale VFETs with channel length down to 4 nm, on-current over 800 A/cm2, and highest on-off ratio up to 2 × 105, which is over two orders of magnitude higher compared to control samples without laminating process. Our study not only represents the optimization of VFETs performance and scalability at the same time, but also offers a method of transfer large-scale oxide arrays, providing interesting implication for ultra-thin vertical devices.

Date: 2024
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DOI: 10.1038/s41467-024-52150-7

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