Feasibility Study of Future HPC Systems for Memory-Intensive Applications

Hiroaki Kobayashi ()
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Hiroaki Kobayashi: Tohoku University

A chapter in Sustained Simulation Performance 2013, 2013, pp 3-11 from Springer

Abstract: Abstract After the successful launch of K-Computer in Japan, the Japanese government started a new R&D program entitled “Feasibility Study of Future HPCI Systems.” In this program, social and scientific demands for HPC in the next 5–10 years will be addressed, and HPC systems that satisfy the demands and key technologies to develop such systems will be discussed and evaluated. Currently, three system design teams get involved in this program, and this article present a HPC project entitled “Feasibility Study of Future HPC Systems for Memory Intensive Applications,” which is conducted by a team of Tohoku University, JAMSTEC and NEC.

Keywords: Memory Bandwidth; Peak Performance; Memory Subsystem; Vector Processor; Roof Line (search for similar items in EconPapers)
Date: 2013
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Persistent link: https://EconPapers.repec.org/RePEc:spr:sprchp:978-3-319-01439-5_1

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DOI: 10.1007/978-3-319-01439-5_1

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