Performance Evaluation of an OpenMP Parallelization by Using Automatic Parallelization Information

Kazuhiko Komatsu (), Ryusuke Egawa (), Hiroyuki Takizawa () and Hiroaki Kobayashi ()
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Kazuhiko Komatsu: Tohoku University/JST CREST, Cyberscience Center
Ryusuke Egawa: Tohoku University/JST CREST, Cyberscience Center
Hiroyuki Takizawa: Tohoku University/JST CREST, Graduate School of Information Sciences
Hiroaki Kobayashi: Tohoku University, Cyberscience Center

A chapter in Sustained Simulation Performance 2014, 2015, pp 119-126 from Springer

Abstract: Abstract To exploit the potential of many core processors, a serial code is generally optimized for a particular compiler called a target compiler, so that the compiler can understand the code structure for automatic parallelization. However, the performance of such a serial code is always not portable to a new system that uses a different compiler. To improve the performance portability, this paper proposes an OpenMP parallelization method by using compiler messages of the target compiler. Since the compiler messages from the target compiler are also useful to identify key loop nests even for the different system, a programmer can use the message to easily parallelize a serial code with low programming effort. Furthermore, programmer’s intention of the optimization can be migrated to other systems through the OpenMP parallelization, which results in high performance portability. The experimental results indicate that the OpenMP codes parallelized by the proposed method can achieve a comparable or even better performance than the automatically parallelized codes by various compilers.

Keywords: Automatic Parallelization; OpenMP Parallelization; Compiler Messages; Target Compiler; Loop Nest Parallelization (search for similar items in EconPapers)
Date: 2015
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Persistent link: https://EconPapers.repec.org/RePEc:spr:sprchp:978-3-319-10626-7_10

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DOI: 10.1007/978-3-319-10626-7_10

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