Hardware Implementation of Floating-Point Arithmetic

Jean-Michel Muller, Nicolas Brunie, Florent de Dinechin, Claude-Pierre Jeannerod, Mioara Joldes, Vincent Lefèvre, Guillaume Melquiond, Nathalie Revol and Serge Torres
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Jean-Michel Muller: CNRS - LIP
Nicolas Brunie: Kalray
Florent de Dinechin: INSA-Lyon - CITI
Claude-Pierre Jeannerod: Inria - LIP
Mioara Joldes: CNRS - LAAS
Vincent Lefèvre: Inria - LIP
Guillaume Melquiond: Inria - LRI
Nathalie Revol: Inria - LIP
Serge Torres: ENS-Lyon - LIP

Chapter Chapter 8 in Handbook of Floating-Point Arithmetic, 2018, pp 267-320 from Springer

Abstract: Abstract Chapter 7 has shown that operations on floating-point numbers are naturally expressed in terms of integer or fixed-point operations on the significand and the exponent. For instance, to obtain the product of two floating-point numbers, one basically multiplies the significands and adds the exponents. However, obtaining the correct rounding of the result may require considerable design effort and the use of nonarithmetic primitives such as leading-zero counters and shifters. This chapter details the implementation of these algorithms in hardware, using digital logic.

Keywords: Significand; Leading Zero Count (LZC); Correct Rounding; Partial Product Array; Sticky Bit (search for similar items in EconPapers)
Date: 2018
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DOI: 10.1007/978-3-319-76526-6_8

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