Architectural Considerations for Exascale Supercomputing

Yasuo Ishii ()
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Yasuo Ishii: NEC Corporation, HPC Division

A chapter in Sustained Simulation Performance 2012, 2013, pp 13-24 from Springer

Abstract: Abstract Towards exascale supercomputing, both academia and industry have started to investigate the future HPC technologies. One of the most difficult challenges is the enhancement of energy efficiency of the computer system. We discuss the energy efficiency of existing architecture in this paper. With the analysis of the performance of the dense matrix–matrix multiplication (DGEMM), we propose the DGEMM-specialized Vector-SIMD architecture that only requires the small number of processor cores and low memory bandwidth. The DGEMM-specialized Vector-SIMD architecture can outperform existing architectures with respect to several metrics, as far as it is dedicated to limited usages, such as the DGEMM calculation. We conclude that this type of discussion will be essential in designing the future computer architecture.

Keywords: Exascale Supercomputers; Last-level Cache; Single Instruction Multiple Thread (SIMT); Data-level Parallelism; Architectural Design Patterns (search for similar items in EconPapers)
Date: 2013
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Persistent link: https://EconPapers.repec.org/RePEc:spr:sprchp:978-3-642-32454-3_2

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DOI: 10.1007/978-3-642-32454-3_2

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