Exploring a Design Space of 3-D Stacked Vector Processors

Ryusuke Egawa (), Jubee Tada () and Hiroaki Kobayashi ()
Additional contact information
Ryusuke Egawa: Tohoku University/JST CREST, Cyberscience Center
Jubee Tada: Yamagata University, Graduate School of Science and Engineering
Hiroaki Kobayashi: Tohoku University/JST CREST, Cyberscience Center

A chapter in Sustained Simulation Performance 2012, 2013, pp 35-49 from Springer

Abstract: Abstract Three dimensional (3-D) technologies have come under the spotlight to overcome limitations of conventional two dimensional (2-D) microprocessor implementations. However, the effect of 3-D integrations with vertical interconnects in future vector processors design is not well discussed yet. In this paper, aiming at exploring the design space of future vector processors, fine and coarse grain 3-D integrations that aggressively employ vertical interconnects are designed and evaluated.

Keywords: Integration Technology; Memory Bandwidth; Arithmetic Unit; Phase Change Random Access Memory; Vector Processor (search for similar items in EconPapers)
Date: 2013
References: Add references at CitEc
Citations:

There are no downloads for this item, see the EconPapers FAQ for hints about obtaining it.

Related works:
This item may be available elsewhere in EconPapers: Search for items with the same title.

Export reference: BibTeX RIS (EndNote, ProCite, RefMan) HTML/Text

Persistent link: https://EconPapers.repec.org/RePEc:spr:sprchp:978-3-642-32454-3_4

Ordering information: This item can be ordered from
http://www.springer.com/9783642324543

DOI: 10.1007/978-3-642-32454-3_4

Access Statistics for this chapter

More chapters in Springer Books from Springer
Bibliographic data for series maintained by Sonal Shukla () and Springer Nature Abstracting and Indexing ().