Implement and Evaluation of Collaborative Optimization on Testing and Mapping For NOC

Zhengfei Jin (), Ying Zhang (), Xiaokai Zhang () and Xin Chen ()
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Zhengfei Jin: Nanjing University of Aeronautics and Astronautics, The College of Electronic and Information Engineering
Ying Zhang: Nanjing University of Aeronautics and Astronautics, The College of Electronic and Information Engineering
Xiaokai Zhang: Aviation Key Laboratory of Science and Technology on Aero Electromechanical System Integration
Xin Chen: Nanjing University of Aeronautics and Astronautics, The College of Electronic and Information Engineering

Chapter Chapter 17 in Transactions on Engineering Technologies, 2019, pp 231-243 from Springer

Abstract: Abstract The efficient application mapping to NoC infrastructure and NoC testing are both important topics for complex SoC chips. This paper proposes a comprehensive optimization scheme of IP cores testing and NoC mapping with the evaluation platform. Associated with the pre-designed test structure, IP cores are partitioned into parallel testing groups to minimize the testing time. The Multi-Objective Genetic Algorithm is adopted to collaboratively optimize testing time and NoC mapping performance and the balance of testing and mapping overheads can be adjusted for specific application. A hardware/software co-design evaluation platform is constructed to verify the optimization effect. The results of simulations and experiments on testing platform with ITC'02 benchmark circuits showed the effectiveness and flexibility of the collaborative testing and mapping optimization for NoC.

Keywords: NoC testing; NoC mapping; Multi-objective Genetic Algorithm; Testing schedule; FPGA; Evaluation platform (search for similar items in EconPapers)
Date: 2019
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DOI: 10.1007/978-981-32-9531-5_17

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