Design and analysis of a sleep and wake-up CMOS low noise amplifier for 5G applications

A. Andrew Roobert () and D. Gracia Nirmala Rani ()
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A. Andrew Roobert: Francis Xavier Engineering College
D. Gracia Nirmala Rani: Thiagarajar College of Engineering

Telecommunication Systems: Modelling, Analysis, Design and Management, 2021, vol. 76, issue 3, No 9, 470 pages

Abstract: Abstract This brief proposes a two-stage cascoded CMOS LNA with common drain envelope detection based power reduction method for the 5G applications of 28 GHz frequency. Dual inductive peaking and stagger tuning techniques are involved to get a 3 dB bandwidth of 2.25 GHz from 26.75 to 29 GHz. Besides, 22 dB of gain is provided by the proposed LNA. Inductive source degeneration helps to reduce the Noise Figure (NF) of the first cascoded stage, and a 2.3 dB of NF is observed in the LNA. The primarily amplified signals from the first cascoded stage are fed to the envelope detector and the second cascoded stage. When the RF signal is received, the envelope detector output will be high, and it turns on the second cascoded stage. In the existing method, the combination of a diode-connected transistor, low pass filter and buffer has been used for the envelope detection. A common drain transistor with an active resistor and capacitor is used in the envelope detection of the proposed method. Here, the power consumption of the LNA is reduced by 25.26% at the sleep mode. The proposed LNA consumes 9.5 mW and 7.1 mW of power from a 1.5 V supply at the active state and sleep state respectively. It requires 0.1235 mm2 of core area in 90 nm technology. Moreover, the behavior of the circuit under process corner variation and temperature variation is analyzed, and Monte–Carlo analysis is performed.

Keywords: CMOS LNA; Envelope detection; 5G applications; Mobile communication; Power reduction (search for similar items in EconPapers)
Date: 2021
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DOI: 10.1007/s11235-020-00729-y

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