A compact memristor emulator for novel IC applications: Its design and experimental validation

Sagar,, Jagveer Singh Verma, Manoj Joshi, Rajeev Kumar Ranjan and Sung-Mo Kang

Chaos, Solitons & Fractals, 2024, vol. 183, issue C

Abstract: Device fabrication with precise operating parameters is challenging and encourages innovation in memristor emulator (MRE) circuit design. This article presents a simple MRE designed using CMOS devices based on a Current Conveyor Transconductance Amplifier (CCTA) as its active element with a few passive components. It is capable of both floating and grounded memristor applications and exhibits effective operation in the MHz frequency range for both incremental and decremental modes of operation, along with the feature allowing electronic tunability. The simulation has been carried out using a Cadence Virtuoso with 0.18 μm process parameters with ±1 V of DC supply. The reliability and resilience of this design have been validated for short-term non-volatility, process corner analyses, temperature fluctuations, and Monte Carlo analysis. In addition, mathematical justification and functional experimental validation of proposed MRE have been achieved using off-the-shelf components. Finally, the MRE circuit's unique non-linear and non-volatile nature has been utilized to implement the Chua's oscillator and an adaptive learning of unicellular organisms as its potential applications.

Keywords: Memristor emulator (MRE); Pinched hysteresis loop (PHL); Nonvolatility; Chua's oscillator; Adaptive learning (search for similar items in EconPapers)
Date: 2024
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Persistent link: https://EconPapers.repec.org/RePEc:eee:chsofr:v:183:y:2024:i:c:s096007792400376x

DOI: 10.1016/j.chaos.2024.114824

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