SoC implementation of a photovoltaic reconfiguration algorithm by exploiting a HLS-based architecture

G. Petrone, F. Serra, G. Spagnuolo and E. Monmasson

Mathematics and Computers in Simulation (MATCOM), 2019, vol. 158, issue C, 520-537

Abstract: The dynamic reconfiguration of photovoltaic arrays is a promising technique for reducing the power drops due to partial shadowing. Some approaches for determining the optimal electrical configuration of the photovoltaic array have been presented in literature. The most encouraging solution is based on the use of stochastic algorithms that can be fruitfully implemented in a system on chip. The computation time takes profit from the available field programmable gate array fabric, where multiple instances of the fitness function can be run in parallel. The use of Vivado High Level Synthesis, to create a Register Transfer Level implementation from C/C++ sources, allows achieving satisfactory results. Coding the algorithm by taking into account the synthesis process, thus resource allocation, scheduling and binding, helps in obtaining a further performance improvement. In this paper a High Level Synthesis approach is used for the systematic exploration of the possible architectures that can be used for implementing the reconfiguration algorithm. Some solutions that differ in terms of computation time and hardware resources used are compared. The target system on chip is a low cost one from Xilinx.

Keywords: High Level Synthesis; Field programmable gate array; Hardware accelerator; Photovoltaic (search for similar items in EconPapers)
Date: 2019
References: View complete reference list from CitEc
Citations: View citations in EconPapers (1)

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Persistent link: https://EconPapers.repec.org/RePEc:eee:matcom:v:158:y:2019:i:c:p:520-537

DOI: 10.1016/j.matcom.2018.12.013

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