Parallel digital neural hardware for controller design

S. Neusser and B. Höfflinger

Mathematics and Computers in Simulation (MATCOM), 1996, vol. 41, issue 1, 149-160

Abstract: A general comparison with regard to speed and size of digital neural hardware on different levels of parallelism results in the design of a fully parallel architecture based on a bit-serial neural hardware model with a new quadratic squashing function. This nonlinear squashing function is well suited for small parallel digital hardware implementations. A cascadable semicustom chip containing six neurons was designed based on this model. This neurochip is used in the hardware implementation of a neurocontroller. The controller is developed for the lateral control of a vehicle and trained from only 6000 samples of human driving behavior recorded on a German federal highway.

Date: 1996
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Persistent link: https://EconPapers.repec.org/RePEc:eee:matcom:v:41:y:1996:i:1:p:149-160

DOI: 10.1016/0378-4754(95)00067-4

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